Data packet routing systems are known that employ the Peripheral Component Interconnect Express system (also referred to herein as the “PCIe system”) for enabling data transfers between an application layer device and a host device over a pair of PCIe links (TX/RX). For example, the application layer device may be a router connected between the PCIe system and a number of client devices. Each PCIe link is a point-to-point serial communication channel connected between a PCIe port of the application layer device and a PCIe port of the host device, allowing the respective devices to transmit/receive PCIe requests such as memory-read/write requests over the respective PCIe links. The PCIe system can handle several different types of data transfers, including posted data transfers such as memory-write data transfers, and non-posted data transfers such as memory-read data transfers. The PCIe system includes a PCIe system core, which is a controller operative to implement the PCIe system protocol, and to identify and resolve the PCIe system protocol layers, including a physical/media access control (mac) layer, a link layer, and a transaction layer. The application layer device can use the PCIe system protocol to implement a variety of data transfer applications through the PCIe links, including, but not limited to, multimedia file transfer applications, real-time video/voice streaming applications, and video conferencing applications.
In a conventional data packet routing system, the application layer device may employ the PCIe system protocol to implement a data transfer application that utilizes a transaction ID-based data packet routing mechanism. Each transaction ID is a 24-bit wide field embedded in a data packet that can be used to provide a unique identifier for a requester of the data packet. For example, in a data packet transfer transaction involving the application layer device and the host device, if the data packet transfer transaction includes a memory-read data transfer that requires an acknowledgment-type data packet (also referred to herein as a “completion data packet”) from the host device, then the application layer device can use information contained in the transaction ID field of each completion data packet to route the data packet to the client device that initiated the data packet transfer transaction. More specifically, the transaction ID field includes a 5-bit tag field (extendible to 8 bits) that contains information defining a tag value for use in identifying the client device, which can initiate one or more data packet transfer transactions within a predetermined period of time. Some or all of these data packet transfer transactions may include memory-read data transfers, requiring corresponding completion data packets from the host device. All such completion data packets received at the application layer device would generally look the same, except for the tag fields included in the transaction IDs of the respective completion data packets. Accordingly, the application layer device can access the information contained in the tag fields to distinguish between the different completion data packets received from the host device, and to identify the client device that initiated the data packet transfer transaction.
In another conventional data packet routing system, a direct memory access (DMA) processing engine may be employed to perform multiple memory-read/write data transfers independently of the system central processing unit (CPU), thereby reducing the overhead of the system CPU. For example, a client device may initiate a data packet transfer transaction including a memory-read data transfer, and the DMA processing engine may prepare a corresponding memory-read request data packet, and transmit the memory-read request data packet to a host device over a PCIe link. In response to receiving the memory-read request data packet, the host device transmits a completion data packet to the DMA processing engine. The DMA processing engine receives the completion data packet from the host device over another PCIe link, and accesses the requested memory-read data contained in the completion data packet for subsequent forwarding to the client device that initiated or is the target of the data packet transfer transaction. The DMA processing engine can identify the client device using the information contained in the transaction ID tag field embedded in the completion data packet.
One drawback of the conventional data packet routing systems described above is that 32 different tag values defined by the information contained in the 5-bit tag field, along with a set of transaction parameters (e.g., routing information, a destination address, etc.) for each tag value, have to be stored in internal memory, thereby expending a significant amount of system resources. Further, following each memory-read request, the tag value contained in each completion data packet has to be compared with the different tag values stored in the internal memory in order to access the proper set of transaction parameters. Such tag processing can require many clock cycles to complete, and, as a result, can significantly impair overall system performance. Moreover, in the conventional data packet routing system that employs the DMA processing engine, such tag processing can place constraints on the number of outstanding memory-read requests that the DMA processing engine might otherwise issue.
It would therefore be desirable to have systems and methods of routing data packets that avoid at least some of the drawbacks of the conventional data packet routing systems described above.